Our team
DVLab (Design Verification Lab) at NTU EE, led by Prof. Chung-Yang (Ric) Huang. Research on formal verification, quantum circuit synthesis and optimization, and EDA.
Semester 115-1
High tech Entrepreneurship and Operation (EEE5031) is a graduate elective at NTU GIIEE taught by Prof. Chung Yang (Ric) Huang, exploring the entrepreneurial journey and business operations in high tech industries, cover…
Semester 114-2
Special Topics on Quantum Design Automation (EEE5065) is a graduate elective at NTU GIIEE introducing the core technologies of Quantum Design Automation (QDA), exploring how electronic design automation (EDA) methods ex…
Semester 114-2
SoC Verification (EEE5023) is a graduate elective at NTU GIIEE introducing formal verification techniques for system on chip designs. The course covers formal modeling and property specification, Binary Decision Diagram…
