Huang Ssu-Wei

Stanley

Master AI for Formal / Formal Verification
Huang Ssu-Wei

About

I am a master’s student in the Graduate Program of Integrated Circuit Design and Automation at National Taiwan University’s Graduate School of Advanced Technology, researching formal verification and AI-assisted verification. I served as a teaching assistant for the System-on-Chip Verification course in Spring 2026.

Research interests

EDA, Formal Verification, SAT/SMT Solvers, and AI-assisted Verification; using LLMs to generate lemmas, invariants, and candidate predicates, then checking their correctness with formal tools.